The present invention relates to a semiconductor integrated circuit memory device, and more particularly, to a semiconductor integrated circuit memory device including a plurality of static type memory cells.
Heretofore, static type memory devices making use of insulated gate field effect transistors (hereinafter abbreviated as IGFET's) were not necessitated to have the sizes of their respective memory cells reduced so small because of the fact that their memory capacities, that is, the number of their memory cells, were small such as 1 kilobits or 4 kilobits. However, as the memory capacity is increased such as 16 kilobits or 64 kilobits, it has naturally become necessary to reduce the cell size. Especially, it is necessary to reduce the size of the respective cells in the direction of extension of word lines (hereinafter called Y-direction). More particularly, in the case of employing a dual-in-line package, even if a memory capacity is increased, the width of the package, that is, the interval between the left and right pin columns has a fixed value such as, for example, 300 mils. Accordingly, it is impossible to increase the size in the same direction of the island sections on which memory elements (chips) are mounted as aligned in the same direction of the above-described package, and hence the size in the same direction of this memory element also cannot be made large even if the memory capacity is increased. On the other hand, taking into consideration the layout of a memory cell forming region and a peripheral circuit region including respective decoder circuits, sense amplifiers, address inverters, etc. within a memory element, the direction of extension of word lines, that is, the Y-direction is the widthwise direction of the above-mentioned package. Accordingly, with respect to the size of each memory cell, size reduction in the Y-direction is more important than size reduction in the direction at right angles to the Y-direction (hereinafter called X-direction). In addition, even if such restriction imposed by a package is not present, it is important to reduce the respective memory cells and thereby realize a high degree of circuit integration.
Here it is to be noted that the principal cause of the fact that the static type memory cell in the prior art could not be reduce to a desired occupation area exists in the layout structure of the respective wiring layers. In more particular, in the prior art with respect to each memory cell, one word line made of a first polycrystalline silicon layer and one of power supply lines, for example, a Vcc line made of a second polycrystalline silicon layer extend in the Y-direction. On the other hand, two data lines made of a first aluminum layer and the other of power supply lines, for example, a ground line made of, also, the first aluminum layer extend in the X-direction. In other words, three lines made of the single aluminum layer must intersect the edge line extending in the Y-direction of one memory cell. In view of a necessary width of each line and a necessary interval between lines, the size of one memory cell in the Y-direction must be large enough to allow the three wiring lines. Therefore, the principal cause of the memory cells in the prior art being unable to be reduced to a desired size was the existence of these three wiring lines with a single aluminium layer.
In addition, as a result of increase of a memory capacity, speed-up of an access speed also must be taken into considerations. In the static type memory element in the prior art, generally a polycrystalline silicon layer was used as a word line. This was due to the presence of the merit that by making use of a part of this layer as a gate electrode, source and drain regions of an IGFET can be formed in a self-alignment manner. However, since a polycrystalline silicon layer cannot have its resistance lowered to a desired extent, restriction is placed on speed-up of an access speed.